Testability Improvement During High-Level Synthesis

Improving testability during the early stages of HighLevel Synthesis (HLS) reduces test hardware overheads, test costs, design iterations, and also improves fault coverage [1]. In this paper, we present a novel register allocation algorithm which is based on weighted graph coloring, targeting testability improvement. 1. Proposed testability model In our register allocation method, we construct an extended conflict graph (ECG) whose vertices are variables and the weight of each edge shows the cost of assigning two endpoint variables of the edge to a register. There are three types of edges in the ECG, an edge with +∞ weight which shows that the corresponding variables cannot be assigned to a single register, positive weight shows that we prefer not to assign these variables to a register, and negative weight shows the preference to assign these variables to a register. CY/OY Enhancement: We place an edge between each primary input (primary output) variable and its compatible intermediate variable, with weight -wco (–wob). Sequential Depth and Loop Reduction: For all compatible variable pairs (vi, vj), which are assigned to the register pair (Ri, Rj), merge the two registers and evaluate Pij (the maximum length of the shortest path between primary inputs and outputs), cij (the length of the longest cycle), and nij (the number of independent cycles). Self-Loop Elimination: To eliminate a self-adjacent loop, we add an edge, whose weight is +wself, between each pairs of input and output variables of a module. The cost of merging two variables (vi ,vj) is calculated as